The IDT723612 is a monolithic high-speed, low-power BiCMOS bi-directional clocked FIFO memory. It supports clock frequencies up to 67 MHz and has read access times as fast as 10ns. Two independent 64 x 36 dual-port SRAM FIFOs on board the chip buffer data in opposite directions. Each FIFO has flags to indicate empty and full conditions and two programmable flags (almost-full and almost-empty) to indicate when a selected number of words is stored in memory. Communication between each port can bypass the FIFOs via two 36-bit mailbox registers. Each mailbox register has a flag to signal when new mail has been stored. Parity is checked passively on each port and may be ignored if not desired. Parity generation can be selected for data read from each port. Two or more devices can be used in parallel to create wider data paths.
The IDT723612 is a clocked FIFO, which means each port employs a synchronous interface. All data transfers through Note: 1. NC - No internal connection a port are gated to the LOW-to-HIGH transition of a port clock by enable signals. The clocks for each port are independent of one another and can be asynchronous or coincident. The enables for each port are arranged to provide a simple bidirectional interface between microprocessors and/or buses with synchronous control.
The full flag (FFA, FFB) and almost-full (AFA, AFB) flag of a FIFO are two-stage synchronized to the port clock that writesdata to its array. The empty flag (EFA, EFB) and almost-empty (AEA, AEB) flag of a FIFO are two stage synchronized to the port clock that reads data from its array. The IDT723612 is characterized for operation from 0°C to 70°C.
Features:
• Free-running CLKA and CLKB can be asynchronous or coincident (simultaneous reading and writing of data on a single clock edge is permitted)• Two independent clocked FIFOs (64 x 36 storage capacity each) buffering data in opposite directions• Mailbox bypass Register for each FIFO• Programmable Almost-Full and Almost-Empty Flags• Microprocessor interface control logic•EFA, FFA, AEA, and AFA flags synchronized by CLKA• EFB, FFB, AEB, and AFB flags synchronized by CLKB• Passive parity checking on each port• Parity generation can be selected for each port• Low-power advanced BiCMOS technology• Supports clock frequencies up to 67 MHz• Fast access times of 10ns• Available in 132-pin plastic quad flat package (PQF) or space-saving 120-pin thin quad flat package (TQFP)• Industrial temperature range (-40oC to +85oC) is available, tested to military electrical specifications
(Absolute) Maximum Ratings:
Symbol
Rating
Commercial
Unit
VCC
Supply Voltage Range
-0.5 to 7
V
VI(2)
Input Voltage Range
-0.5 to VCC+0.5
V
VO(2)
Output Voltage Range
-0.5 to VCC+0.5
V
IIK
Input Clamp Current, (VI < 0 or VI > VCC)
±20
mA
IOK
Output Clamp Current, (VO < 0 or VO > VCC)
±50
mA
IOUT
Continuous Output Current, (VO = 0 to VCC)
±50
mA
ICC
Continuous Current Through VCC or GND
±500
mA
TA
Operating Free Air Temperature Range
0 to 70
°C
TSTG
Storage Temperature Range
-65 to 150
°C
Notes: 1. Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under "Recommended Operating Conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 2. The input and output voltage ratings may be exceeded provided the input and output current ratings are observed.
